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STK14C88 32 k x 8 autostore nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-52038 rev. *c revised march 30, 2011 features 25, 35, 45 ns read access and r/w cycle time unlimited read/write endurance automatic nonvolatile store on power loss nonvolatile store under hardware or software control automatic recall to sram on power up unlimited recall cycles 1-million store cycles 100-year nonvolatile data retention single 5 v+ 10% power supply commercial, industrial, military temperatures 32-pin 300 mil soic (rohs-compliant) 32-pin cdip and lcc packages description the cypress STK14C88 is a 256 kb fast static ram with a nonvolatile quantum trap stor age element included with each memory cell. the sram provides the fast a ccess and cycle times, ease of use, and unlimited read and write endurance of a normal sram. data automatically transfers to the nonvolatile storage cells when power loss is detected (the store operation). on power up, data is automatically restored to the sram (the recall operation). both store and recall operations are also available under software control. the cypress nvsram is the firs t monolithic nonvolatile memory to offer unlimited writes and reads . it is the highest performance, most reliable nonvolatile memory available. a 0 a 1 a 2 a 3 a 4 a 10 column i/o column dec static ram array 512 x 512 row decoder input buffers quantum trap 512 x 512 store/ recall control store recall power control a 5 a 6 a 7 a 8 a 9 a 11 a 12 a 13 a 14 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 software detect g e w hsb v ccx v cap a 0 - a 13 logic block diagram [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 2 of 20 contents pin configurations ........................................................... 3 pin descriptions ............................................................... 3 absolute maximum ratings ............................................ 4 dc characteristics ........................................................... 4 ac test conditions .......................................................... 5 capacitance ...................................................................... 5 sram read cycles #1 and #2 ......................................... 6 sram write cycle #1 and #2 ........................................... 7 hardware mode selection ................................................ 8 hardware store cycle ................................................... 8 autostore/power up recall ......................................... 9 software store/recall mode selection .................. 10 software-controlled store/recall cycle ................ 10 nvsram operation ......................................................... 11 noise considerations ..................................................... 11 sram read ..................................................................... 11 sram write ..................................................................... 11 power up recall ......................................................... 11 software nonvolatile store ... ...................................... 11 software nonvolatile recall ...................................... 11 autostore mode .............................................................. 11 autostore inhibit mode ................................................ 12 hsb operation ................................................................ 12 best practices ................................................................. 13 preventing stores ....................................................... 13 hardware protect ............................................................ 13 low average active power ............................................ 13 ordering information ...................................................... 14 commercial and industrial ordering information ....... 14 military ordering information ..................................... 15 package diagrams .......................................................... 16 acronyms ........................................................................ 19 document conventions ................................................. 19 units of measure ....................................................... 19 document history page ................................................. 20 sales, solutions, and legal information ...................... 20 worldwide sales and design s upport ......... .............. 20 products .................................................................... 20 psoc solutions ......................................................... 20 [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 3 of 20 pin configurations figure 1. pin diagram - 32-pin 300 mil soic/cdip figure 2. pin diagram - 32-pin 450 mil lcc a 14 a 12 a 7 a 6 dq 0 dq 1 dq 2 a 3 a 2 a 1 v cap a 13 a 8 a 9 a 11 a 10 dq 7 dq 6 v ss a 0 nc 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 e a 5 nc a 4 32 31 30 29 v cc hsb w dq 5 dq 3 dq 4 g (top) a 6 a 3 a 5 a 4 dq 6 dq 5 dq 3 dq 4 dq 0 a 2 a 1 a 0 dq 1 dq 2 v ss a 10 dq 7 a 8 a 9 a 11 nc nc a 13 w a 14 a 12 a 7 v cap hsb v ccx e g (top) pin descriptions pin name i/o description a 14 -a 0 input address: the 15 address inputs select one of 32,768 bytes in the nvsram array. dq 7 -dq 0 i/o data: bi-directional 8-bit data bus for accessing the nvsram. e input chip enable: the active low e input selects the device. w input write enable: the active low w enables data on the dq pins to be written to the address location latched by the falling edge of e. g input output enable: the active low g input enables the data output buffers during read cycles. de-asserting g high caused the dq pins to tristate. v cc power supply power: 5.0v, + 10%. hsb i/o hardware store busy : when low this output indicates a store is in progress. when pulled low external to the chip, it initiates a nonvolatile store operation. a weak pull up resistor keeps this pin high if not connected. (optional connection). v cap power supply autostore capacitor: supplies power to nvsram during power loss to store data from sram to nonvolatile storage elements. v ss power supply ground. nc no connect unlabeled pins have no internal connections. [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 4 of 20 absolute maximum ratings voltage on input relative to ground...............?0.5 v to 7.0 v voltage on input relative to v ss .........?0.6 v to (v cc + 0.5 v) voltage on dq 0-7 or hsb ....................?0.5 v to (v cc + 0.5 v) temperature under bias ............................. ?55 ? c to 125 ?c storage temperature .................................. ?65 ? c to 150 ?c power dissipation...................... ...................................... 1 w dc output current (1 output at a time, 1s duration).... 15 ma note stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc characteristics over the operating range (v cc = 5.0 v 10%) [4] symbol parameter commercial industrial/ military unit notes min max min max i cc 1 [1] average v cc current ? 97 80 70 ? 100 85 70 ma ma ma t avav = 25 ns t avav = 35 ns t avav = 45 ns i cc 2 [2] average v cc current during store ? 3 ? 3 ma all inputs don?t care, v cc = max i cc 3 [1] average v cc current at t avav = 200 ns 5v, 25c, typical ?10?10maw ? (v cc ? 0.2v) all others cycling, cmos levels i cc 4 [2] average v cap current during autostore cycle ? 2 ? 2 ma all inputs don?t care i sb 1 [3] average v cc current (standby, cycling ttl input levels) ?30 25 22 ?31 26 23 ma ma ma t avav = 25 ns, e ? v ih t avav = 35 ns, e ? v ih t avav = 45 ns, e ? v ih i sb 2 [3] v cc standby current (standby, stable cmos input levels) ?1.5?1.5mae ? (v cc ? 0.2v) all others v in ? 0.2v or ? (v cc ? 0.2v) i ilk input leakage current ? ? 1? ? 1 ? av cc = max v in = v ss to v cc i olk off-state output leakage current ? ? 5? ? 5 ? av cc = max v in = v ss to v cc , e or g ?? v ih v ih input logic ?1? voltage 2.2 v cc + 0.5 2.2 v cc +0.5 v all inputs v il input logic ?0? voltage v ss ? .5 0.8 v ss ? .5 0.8 v all inputs v oh output logic ?1? voltage 2.4 ? 2.4 ? v i out = ? 4 ma except hsb v ol output logic ?0? voltage ? 0.4 ? 0.4 v i out = 8 ma except hsb v bl logic ?0? voltage on hsb output ? 0.4 ? 0.4 v i out = 3 ma t a operating temperature 0 70 - 40/-55 85/125 ?c notes 1. i cc1 and i cc3 are dependent on output loading and cycle rate. the spec ified values are obtained with outputs unloaded. 2. i cc2 and i cc4 are the average currents required for the duration of the respective store cycles (t store ). 3. e ? v ih does not produce standby current levels until any nonvolatile cycle in progress has timed out. 4. v cc reference levels throughout this data sheet refer to v cc if that is where the power s upply connection is made, or v cap if v cc is connected to ground. [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 5 of 20 ac test conditions figure 3. ac output loading capacitance parameter [5] description test conditions max unit conditions c in input capacitance t a = 25 ? c, f = 1 mhz, 5 pf ? v = 0 to 3 v c out output capacitance 7 pf ? v = 0 to 3 v input pulse levels.................................................... 0 v to 3 v input rise and fall times ............................................... < 5 ns input and output timing referenc e levels .......... ............. 1.5 v output load........................................................ see figure 3 480 ohms 30 pf 255 ohms 5.0 v including scope and output fixture note 5. these parameters are guaranteed but not tested. [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 6 of 20 figure 5. sram read cycle 2: e and g controlled [6] sram read cycles #1 and #2 (vcc = 5.0 v 10%) [4] no. symbols parameter STK14C88-25 STK14C88-35 STK14C88-45 unit min max min max min max #1, #2 alt. 1t elqv t acs chip enable access time ? 25 ? 35 ? 45 ns 2t avav [6] , t eleh [6] t rc read cycle time 25 35 ? 45 ? ns 3t avqv 7 t aa address access time ? 25 ? 35 ? 45 ns 4t glqv t oe output enable to data valid ? 10 ? 15 ? 20 ns 5t axqx [7] t oh output hold after address change 5 ? 5 ? 5 ? ns 6t elqx t lz address change or chip enable to output active 5?5?5?ns 7t ehqz [8] t hz address change or chip disable to output inactive ?10?13?15ns 8t glqx t olz output enable to output active 0 ? 0 ? 0 ? ns 9t ghqz [8] t ohz output disable to output inactive ? 10 ? 13 15 ns 10 t elicch [5] t pa chip enable to power active 0 ? 0 0 ? ns 11 t ehiccl [5] t ps chip disable to power standby ? 25 35 ? 45 ns figure 4. sram read cycle 1: address controlled [ 6 , 7 ] notes 6. w and hsb must be high during sram read cycles. 7. i/o state assumes e and g < v il and w ? v ih ; device is continuously selected. 8. measured 200 mv from steady state output voltage. data valid 5 t axqx 3 t avqv dq (data out) address 2 t avav 2 29 11 7 9 10 8 4 3 6 1 [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 7 of 20 sram write cycle #1 and #2 (vcc = 5.0v 10%) [4] no. symbols parameter STK14C88-25 STK14C88-35 STK14C88-45 unit min max min max min max #1 #2 alt. 12 t avav t avav t wc write cycle time 25 ? 35 ? 45 ? ns 13 t wlwh t wleh t wp write pulse width 20 ? 25 ? 30 ? ns 14 t elwh t eleh t cw chip enable to end of write 20 ? 25 ? 30 ? ns 15 t dvwh t dveh t dw data setup to end of write 10 ? 12 ? 15 ? ns 16 t whdx t ehdx t dh data hold after end of write 0 ? 0 ? 0 ? ns 17 t avwh t aveh t aw address setup to end of write 20 ? 25 ? 30 ? ns 18 t avwl t avel t as address setup to start of write 0 ? 0 ? 0 ? ns 19 t whax t ehax t wr address hold after end of write 0 ? 0 ? 0 ? ns 20 t wlqz [8, 9] t wz write enable to output disable ? 10 ? 13 ? 15 ns 21 t whqx t ow output active after end of write 5 ? 5 ? 5 ? ns figure 6. sram write cycle 1: w controlled [10, 11] figure 7. sram write cycle 2: e controlled [10, 11] data out e address w data in previous data 12 t avav 13 t whdx 19 t whax 13 t wlwh 18 t avwl 17 t avwh data valid 20 t wlqz 15 t dvwh high impedance 21 t whqx 14 t elwh 12 t avav 16 t ehdx 13 t wleh 19 t ehax 18 t avel 17 t aveh data valid 15 t dveh high impedance 14 t eleh data out e address w data in notes 9. if w is low when e goes low, the outputs remain in the high impedance state. 10. e or w must be ? v ih during address transitions. 11. hsb must be high during sram write cycles. [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 8 of 20 hardware mode selection e w hsb a 13 - a 0 (hex) mode i/o power notes h x h x not selected output high z standby ? l h h x read sram output data active 19 l l h x write sram input data active ? x x l x nonvolatile store output high z l cc 2 12 hardware store cycle no. symbols parameter STK14C88 units notes standard alternate min max 22 t store t hlhz store cycle duration ? 10 ms 13 23 t delay t hlqz time allowed to complete sram cycle 1 ? ? s13 24 t recover t hhqx hardware store high to inhibit off ? 700 ns 13, 14 25 t hlhx hardware store pulse width 15 ? ns ? 26 t hlbl hardware store low to store busy ? 300 ns ? figure 8. hardware store cycle data valid hsb (in) data valid 25 t hlhx 23 t delay 22 t store 24 t recover high impedance 27 t hlbl high impedance dq (data out) hsb (out) notes 12. hsb store operation occurs only if an sram write is done since the last nonvolatile cycle. after the store (if any) completes, the part goes into standby mode, inhibiting all operations until hsb rises 13. e and g low, w high for output behavior. 14. t recover is only applicable after t store is complete. [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 9 of 20 autostore/power up recall no. symbols parameter STK14C88 unit notes standard alt. min max 27 t restore power up recall duration ? 550 ? s15 28 t store t hlhz store cycle duration ? 10 ms 13, 16 29 t vsbl low voltage trigger (v switch ) to hsb low ? 300 ns 11 30 t delay t blqz time allowed to complete sram cycle 1? ? s13 31 v switch low voltage trigger level 4.0 4.5 v ? 32 v reset low voltage reset level ? 3.6 v ? figure 9. autost ore/power up recall 31 t delay 30 t vsbl power up recall brown out no store (no sram writes) no recall (v cc did not go below v reset ) brown out autostore no recall (v cc did not go below v reset ) brown out autostore recall when v cc returns above v switch autostore hsb w 29 t store 28 t restore power up recall 31 v switch 27 v reset v cc dq (data out) notes 15. t restore starts from the time v cc rises above v switch . 16. hsb is asserted low for 1 ? s when v cap drops through v switch . if an sram write has not taken place since the last nonvolatile cycle, hsb is released and no store takes place. [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 10 of 20 software store/recall mode selection e w a 13 - a 0 (hex) mode i/o power notes l h 0e38 31c7 03e0 3c1f 303f read sram read sram read sram read sram read sram output data output data output data output data output data active 13, 17, 18, 19 0fc0 nonvolatile store output high z i cc2 l h 0e38 31c7 03e0 3c1f 303f 0c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output high z active 13, 17, 18, 19 software-controlled store/recall cycle no. symbols parameter STK14C88-25 STK14C88-35 STK14C88-45 unit notes standard alt. min max min max min max 33 t avav t rc store/recall initiation cycle time 35 ? 45 ? 55 ? ns 13 34 t avel t as address setup time 0 ? 0 ? 0 ? ns 20, 21 35 t eleh t cw clock pulse width 25 ? 30 ? 35 ? ns 20, 21 36 t elax address hold time 20 ? 20 ? 20 ? ns 20, 21 37 t recall recall duration ? 20 ? 20 ? 20 ? s? figure 10. e controlled software store/recall cycle [21] notes 17. the six consecutive addresses must be in the order listed. w must be high during all six consecutive e controlled cycles to enable a nonvolatile cycle. 18. while there are 15 addresses on the STK14C88, only the lower 14 are used to control software modes. 19. i/o state assumes g < v il . activation of nonvolatile cycles does not depend on state of g . 20. the software sequence is clocked on the falling edge of e controlled reads without involving g (double clocking aborts the sequence). 21. the six consecutive addresses must be in the order listed in the software store/recall mode selection table: (0e38, 31c7, 03 e0, 3c1f, 303f, 0fc0) for a store cycle or (0e38, 31c7, 03e0, 3c1f, 303f, 0c63) for a recall cycle. w must be high during all six consecutive cycles. data valid high impedance address #6 address #1 data valid 33 t avav data valid dq (data e address 29 37 t store / t recall 33 t avav 34 t avel 35 t eleh 36 t elax [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 11 of 20 nvsram operation the STK14C88 has two separate modes of operation: sram mode and nonvolatile mode. in sram mode, the memory operates as a standard fast stat ic ram. in nonvolatile mode, data is transferred from sram to nonvolatile elements (the store operation) or from nonvolatile elements to sram (the recall operation). in this mode, sram functions are disabled. noise considerations the STK14C88 is a high speed memory and so must have a high frequency bypass capacitor of approximately 0.1 ? f connected between v cap and v ss , using leads and traces that are as short as possible. as with all high speed cmos ics, careful routing of power, ground, and signals helps to prevent noise problems. sram read the STK14C88 performs a read cycle whenever e and g are low, and w and hsb are high. the address specified on pins a 0-14 determines which of the 32, 768 data bytes are accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t avqv (read cycle #1). if the read is initiated by e or g , the outputs are valid at t elqv or at t glqv , whichever is later (read cycle #2). the data outputs repeatedly respond to address changes within the t avqv access time without the need for transitions on any control input pins, and remain valid until another address change or until e or g is brought high, or w or hsb is brought low. sram write a write cycle is performed whenever e and w are low, and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either e or w goes high at the end of the cycle. the data on the common i/o pins dq 0-7 are written into the memory if it is valid t dvwh before the end of a w controlled write or t dveh before the end of an e controlled write. keep g high during the entire write cycle to avoid data bus contention on common i/o lines. if g is left low, internal circuitry turns off the output buffers t wlqz after w goes low. power up recall during power up, or after any low power condition (v cap < v reset ), an internal recall request is latched. when v cap again exceeds the sense voltage of v switch , a recall cycle is automatically initiated and takes t restore to complete. if the STK14C88 is in a write state at the end of power up recall, the sram data will be corrupted. to avoid this, a 10 kohm resistor should be connected either between w and system v cc or between e and system v cc . software nonvolatile store the STK14C88 software store cycle is initiated by executing sequential e controlled read cycles from six specific address locations. during the store cycl e an erase of the previous nonvolatile data is first performed, followed by a program of the nonvolatile elements. the program operation copies the sram data into nonvolatile memory. w hen a store cycle is initiated, further input and output are dis abled until the cycle is completed. because a sequence of reads from specific addresses is used for store initiation, it is import ant that no other read or write accesses intervene in the sequence, or the sequence will be aborted and no store or recall takes place. to initiate the software st ore cycle, the following read sequence must be performed: 1. read address 0e38 (hex) valid read 2. read address 31c7 (hex) valid read 3. read address 03e0 (hex) valid read 4. read address 3c1f (hex) valid read 5. read address 303f (hex) valid read 6. read address 0fc0 (hex) initiate store cycle the software sequence must be clocked with e controlled reads. after the sixth address in the sequence is entered, the store cycle commences and the chip is disabled. use only read cycles in the sequence, although it is not necessary that g be low for the sequence to be valid. after the tstore cycle time is fulfilled, the sram is again activated for read and write operation. software nonvolatile recall a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of e controlled read operations must be performed: 1. read address 0e38 (hex) valid read 2. read address 31c7 (hex) valid read 3. read address 03e0 (hex) valid read 4. read address 3c1f (hex) valid read 5. read address 303f (hex) valid read 6. read address 0c63 (hex) initiate recall cycle internally, recall is a two step procedure. first, the sram data is cleared, and second, the nonvolatile information is transferred into the sram cells. after the t recall cycle time, the sram is again ready for read and write operations. the recall operation in no way alters the data in the nonvolatile elements. the nonvolatile data can be recalled an unlimited number of times. autostore mode the STK14C88 can be powered in one of three modes. during normal autostore operation, the STK14C88 draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. after power up, when the voltage on the v cap pin drops below v switch , the part automatically disconnects the v cap pin from v cc and initiate a store operation. [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 12 of 20 figure 11 shows the proper connection of capacitors for automatic store operation. a charge storage capacitor having a capacity of between 68 f and 220 f (20%) rated at 6v should be provided. in system power mode, both v cc and v cap are connected to the + 5v power supply without the 68 f capacitor. in this mode, the autostore function of the STK14C88 operates on the stored system charge as power goes dow n. the user must, however, guarantee that v cc does not drop below 3.6v during the 10 ms store cycle. if an automatic store on power loss is not required, then v cc can be tied to ground and + 5v applied to v cap ( figure 12 ). this is the autostore inhibit mode, in which the autostore function is disabled. if the STK14C88 is oper ated in this configuration, refer- ences to v cc should be changed to v cap throughout this data sheet. in this mode, store operations may be triggered through software control or the hsb pin. to enable or disable autostore using an i/o port pin, see preventing stores on page 13 . to prevent unneeded store operations, automatic stores and those initiated by externally driving hsb low are ignored unless at least one write opera tion has taken place since the most recent store or recall cycle. software initiated store cycles are performed regardless of whether a write operation has taken place. if the power supply drops faster than 20 ms/volt before v cc reaches v switch , then a 2.2 ohm resistor should be inserted between v cc and the system supply to avoid momentary excess of current between v cc and v cap . figure 11. autostore mode autostore inhibit mode if an automatic store on power loss is not required, then v cc can be tied to ground and system power applied to v cap (figure 12). this is the autostore inhibit mode, in which the autostore function is disabled. if the STK14C88 is operated in this config- uration, references to v cc should be changed to v cap throughout this data sheet. in this mode, store operations may be triggered through software control. it is not permissible to change between these three options ?on the fly.? figure 12. autostore inhibit mode hsb operation the STK14C88 provides the hsb pin for controlling and acknowledging the store operations. the hsb pin can be used to request a hardware st ore cycle. when the hsb pin is driven low, the STK14C88 conditionally initiates a store operation after t delay ; an actual store cycle only begins if a write to the sram took place since the la st store or recall cycle. the hsb pin has a very resistive pull up and is internally driven low to indicate a busy condition when the store (initiated by any means) is in progress. pull up this pin with an external 10 kohm resistor to v cap if hsb is used as a driver. sram read and write operations that are in progress when hsb is driven low by any means are gi ven time to complete before the store operation is initiated. after hsb goes low, the STK14C88 continues sram operations for t delay . during t delay , multiple sram read operations may take place. if a write is in progress when hsb is pulled low it is allowed a time, tdelay, to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. the hsb pin can be used to synchronize multiple STK14C88s while using a single larger capacitor. to operate in this mode, the hsb pin should be connected together to the hsb pins from the other STK14C88s. an external pull up resistor to + 5v is required because hsb acts as an open drain pull down. the v cap pins from the other STK14C88 parts can be tied together and share a single capacitor. the capaci tor size must be scaled by the number of devices connected to it. when any one of the STK14C88s detects a power loss and asserts hsb , the common hsb pin causes all parts to request a store cycle (a store takes place in those STK14C88s that are written since the last nonvolatile cycle). during any store operation, regardless of how it was initiated, the STK14C88 continues to drive the hsb pin low, releasing it only when the store is complete. upon completion of the store operation the STK14C88 remains disabled until the hsb pin returns high. if hsb is not used, leave it unconnected. 1 16 32 31 17 68 ? f 6v, 20% 0.1 ? f bypass 30 + 10k ? 10k ?? 17 1 16 32 31 30 bypass 0.1f 10k? 10k? [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 13 of 20 best practices nvsram products have been used ef fectively for over 15 years. while ease-of-use is one of the product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in an nvsram are programmed on the test floor during final test and quality assurance. incoming inspection routines at customer or contract manufacturer?s sites sometimes reprogram these values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. the end product?s firmware should not assume an nv array is in a set programmed state. routines that check memory content values to determine first time system configuration, cold or warm boot status, and so on should always program a unique nv pattern (for example, comp lex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system routines work consistently. power up boot firmware routines should rewrite the nvsram into the desired state (such as autostore enabled). while the nvsram is shipped in a preset state, best practice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs, incoming inspection routines, and so on). the v cap value specified in this data sheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the max v cap value because the nvsram internal algorithm calculates v cap charge time based on this max v cap value. customers who want to use a larger v cap value to make sure there is extra store charge and store time should discuss their v cap size selection with cypress to understand any impact on the v cap voltage level at the end of a t recall period. preventing stores the store function can be disabled on the fly by holding hsb high with a driver capable of sourcing 30 ma at a v oh of at least 2.2v, because it must overpower the internal pull down device that drives hsb low for 20 ms at the onset of a store. when the STK14C88 is connected fo r autostore operation (system v cc connected to v cc and a 68 uf capacitor on v cap ) and v cc crosses v switch on the way down, the STK14C88 attempts to pull hsb low; if hsb does not actually get below v il , the part stops trying to pull hsb low and abort the store attempt. hardware protect the STK14C88 offers hardware pr otection against inadvertent store operation and sram writes during low voltage condi- tions. when v cap < v switch , all externally initiated store operations and sram writes are inhibited. autostore can be completely disabled by tying v cc to ground and applying + 5v to v cap . this is the autostore inhibit mode; in this mode stores are only init iated by explicit request using either the software sequence or the hsb pin. low average active power the STK14C88 draws significantly less current when it is cycled at times longer than 50 ns. figure 13 shows the relationship between i cc and read cycle time. worst case current consumption is shown for both cmos and ttl input levels (commercial temperature range, v cc = 5.5v, 100% duty cycle on chip enable). figure 14 shows the same relationship for write cycles. if the chip enable duty cycle is less than 100%, only standby current is drawn when th e chip is disabled. the overall average current drawn by the STK14C88 depends on the following items: cmos vs. ttl input levels the duty cycle of chip enable the overall cycle rate for accesses the ratio of reads to writes the operating temperature the v cc level i/o loading. figure 13. icc (max) reads figure 14. icc (max) writes 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma) 0 20 40 60 80 100 50 100 150 200 cycle time (ns) ttl cmos average active current (ma) [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 14 of 20 ordering information these parts are not recommended for new designs. part number description access times temperature STK14C88-nf25 5v 32kx8 autostore nvsram soic32-300 25 ns commercial STK14C88-nf35 5v 32kx8 autostore nvsram soic32-300 35 ns commercial STK14C88-nf45 5v 32kx8 autostore nvsram soic32-300 45 ns commercial STK14C88-nf25tr 5v 32kx8 autostore nvsram soic32-300 25 ns commercial STK14C88-nf35tr 5v 32kx8 autostore nvsram soic32-300 35 ns commercial STK14C88-nf45tr 5v 32kx8 autostore nvsram soic32-300 45 ns commercial STK14C88-nf25i 5v 32kx8 autostore nvsram soic32-300 25 ns industrial STK14C88-nf35i 5v 32kx8 autostore nvsram soic32-300 35 ns industrial STK14C88-nf45i 5v 32kx8 autostore nvsram soic32-300 45 ns industrial STK14C88-nf25itr 5v 32kx8 autostore nvsram soic32-300 25 ns industrial STK14C88-nf35itr 5v 32kx8 autostore nvsram soic32-300 35 ns industrial STK14C88-nf45itr 5v 32kx8 autostore nvsram soic32-300 45 ns industrial STK14C88-c45i 5v 32kx8 autostore nv sram cdip32-300 45 ns industrial STK14C88-5l35m 5v 32kx8 autostore nvsram lcc32-300 35 ns military STK14C88-5l45m 5v 32kx8 autostore nvsram lcc32-300 45 ns military STK14C88-5c35m 5v 32kx8 autostore nvsram cdip32-300 35 ns military STK14C88-5c45m 5v 32kx8 autostore nvsram cdip32-300 45 ns military STK14C88-5k35m 5v 32kx8 autostore nvsram cdip32-300 35 ns military STK14C88-5k45m 5v 32kx8 autostore nvsram cdip32-300 45 ns military commercial and industri al ordering information speed: 25 = 25 ns 35 = 35 ns STK14C88 - n f 45 i tr temperature range: package 45 = 45 ns packaging option: blank = tube tr = tape and reel i - industrial (-40 to 85c) blank = commercial (0 to 70c) lead finish f = 100% sn (matte tin) n = plastic 32-pin 300 mil soic c = ceramic 32-pin 300 mil cdip l = ceramic 32-pad lcc [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 15 of 20 military ordering information access time STK14C88 - 5 c 45 m temperature range m = military (-55 to 125 ? c) 35 = 35 ns 45 = 45 ns package l=ceramic 32-pad lcc c=ceramic 32-pin 300 mil cdip k=ceramic 32-pin 300 mil cdip with solder dip finish retention / endurance 5 = military (10 5 cycles) [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 16 of 20 package diagrams figure 15. 32-pin 300 mil soic gull wing (51-85127) pin 1 id seating plane 1 16 17 32 dimensions in inches[mm] min. max. 0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642] 0.050[1.270] typ. 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.0100[0.254] 0.006[0.152] 0.012[0.304] 0.021[0.533] 0.041[1.041] 0.026[0.660] 0.032[0.812] 0.004[0.101] reference jedec mo-119 part # s32.3 standard pkg. sz32.3 lead free pkg. 0.014[0.355] 0.020[0.508] 0.810[20.574] 0.822[20.878] 51-85127 *b [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 17 of 20 figure 16. 32-pin 300 mi l side braze dil (001-51694) package diagrams (continued) 001-51694 *a [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 18 of 20 figure 17. 32-pin 450 mil ceramic lcc (51-80068) package diagrams (continued) .045 .055 .055 .045 .045 .055 .064 .090 .442 .458 .540 .560 .022 .028 pin 1 .009 r. 32 places dimensions in inches min. max. .080 .060 51-80068 *a [+] feedback not recommended for new designs
STK14C88 document number: 001-52038 rev. *c page 19 of 20 acronyms document conventions units of measure acronym description nvsram nonvolatile static random access memory ssop shrink small-outline package soic small-outline integrated circuit tsop ii thin small outline package fbga fine-pitch ball grid array rohs restriction of hazardous substances i/o input/output cmos complementary metal oxide semiconductor eia electronic industries alliance rwi read and write inhibited symbol unit of measure c degrees celsius hz hertz kbit 1024 bits khz kilohertz k? kilo ohms ? a microamperes ma milliampere ? f microfarads mhz megahertz ? s microseconds ms millisecond ns nanoseconds pf picofarads v volts ? ohms w watts [+] feedback not recommended for new designs
document number: 001-52038 rev. *c revised march 30, 2011 page 20 of 20 all products and company names mentioned in this document may be the trademarks of their respective holders. STK14C88 ? cypress semiconductor corporation, 2009-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. document history page sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document title: STK14C88 32 k x 8 autostore nvsram document number: 001-52038 rev. ecn no. orig. of change submission date description of change ** 2668632 gvch 03/04/2009 new data sheet *a 2718242 gvch 06/12/09 ordering inform ation description: corrected typo *b 2821358 gvch 12/04/2009 added note in ordering information mentioning that these parts are not recommended for new designs. added ?not recommended for new designs? watermark in the pdf. added contents on page 2. *c 3210316 gvch 03/30/2011 moved contents of page 14 to page 10. updated package diagram. added acronyms and document conventions. [+] feedback not recommended for new designs

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